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numicro ? m052/m054 bn data sheet arm cortex ? - m0 32 - bit microcontroller publication release date: mar. 19 , 20 1 2 - 1 - revision v 1.01 numicro ? family m052/m054 bn data sheet http://
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 2 - revision v 1.01 table of contents 1 general description 6 2 features 7 3 block diagram 11 4 selection table 12 5 pin configuration 13 5.1 qfn 33 pin 13 5.2 lqfp 48 pin 14 5.3 pin description 15 6 functional descripti on 19 6.1 arm? cortex? 19 6.2 system manager 21 6.2.1 overview 21 6.2.2 system reset 21 6.2.3 system power architecture 22 6.2.4 whole system memory map 23 6.2.5 whole system memory mapping table 25 6.2.6 system timer (systick) 25 6.2.7 nested vectored interrupt controller (nvic) 27 6.3 clock controller 28 6.3.1 overview 28 6.3.2 clock generator block diagram 28 6.3.3 system clock & systick clock 30 6.3.4 ahb clock source select 31 6.3.5 peripherals clock source select 32 6.3.6 power down mode (deep sleep mode) clock 33 6.3.7 frequency divider output 33 6.4 general pur pose i/o 35 6.4.1 overview 35 6.5 i 2 c serial interface controller (master/slave) 37 6.5.1 overview 37 6.5.2 features 38 6.6 pwm generator and capture timer 39 6.6.1 overview 39 6.6.2 features 40 6.7 serial peripheral interface (spi) 41 6.7.1 overview 41 6.7.2 features 41 6.8 timer controller 42 6.8.1 overview 42
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 3 - revision v 1.01 6.8.2 features: 42 6.9 watchdog timer (wdt) 43 6.9.1 overview 43 6.9.2 features 44 6.10 uart interface controller (uart) 45 6.10.1 overview 45 6.10.2 features 47 6.11 analog - to - digital converter (ad c) 48 6.11.1 overview 48 6.11.2 features 48 6.12 external bus in terface (ebi) 49 6.12.1 overview 49 6.12.2 features 49 6.13 flas h memory controller (fmc) 50 6.13.1 overview 50 6.13.2 features 50 7 typical application circuit 51 8 electrical character istics 52 8.1 absolute maximum ratings 52 8.2 dc electrical characteristics 53 8.3 ac electrical characteristics 57 8.3.1 external cry stal 57 8.3.2 external oscillator 57 8.3.3 typical crystal application circuits 58 8.3.4 internal 22.1184 mhz rc oscillator 59 8.3.5 internal 10khz rc oscillator 59 8.4 analog characteristics 60 8.4.1 specification of 12 - bit saradc 60 8.4.2 specification of ldo & power management 61 8.4.3 specification of low voltage reset 62 8.4.4 specification of brown - out detector 62 8.4.5 speci fication of power - on reset (5v) 62 8.4.6 specification of temperature sensor 63 8.4.7 specification of comparator 63 8.5 flash dc electrical characteristics 64 9 p ackage dimensions 65 9.1 lqfp - 48 (7x7x1.4mm 2 footprint 2.0mm) 65 9.2 qfn - 33 (5x5 mm 2 , thickness 0.8mm, pitch 0.5 mm) 66 10 revision history 67
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 4 - revision v 1.01 list of figures figure 3 - 1 numicro ? figure 4 - 1 numicro ? figure 5 - 1 numicro ? figure 5 - 2 numicro ? figure 6 - 1 functional block diagram ................................ ................................ ............................. 19 figure 6 - 2 numicro m05 1 ? figure 6 - 3 clock generator block diagram ................................ ................................ ..................... 29 figure 6 - 4 system clock block diagram ................................ ................................ ....................... 30 figure 6 - 5 systick clock control block di agram ................................ ................................ ........... 30 figure 6 - 6 ahb clock source for hclk ................................ ................................ ........................ 31 figure 6 - 7 peripherals clock source select for pclk ................................ ................................ .. 32 figure 6 - 8 clock source of frequency divider ................................ ................................ .............. 33 figure 6 - 9 block diagram of frequency divider ................................ ................................ ............ 34 figure 6 - 10 push - pull output ................................ ................................ ................................ ......... 35 figure 6 - 11 open - drain output ................................ ................................ ................................ ..... 36 figure 6 - 12 quasi - bidirectional i/o mode ................................ ................................ ...................... 36 figure 6 - 13 i 2 c bus timing ................................ ................................ ................................ ............ 37 figure 6 - 14 timing of interrupt and reset signal ................................ ................................ .......... 44 figure 8 - 1 typical crystal application circuit ................................ ................................ ................ 58
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 5 - revision v 1.01 list of table s table 4 - 1 numicro m051 series product selection guide ................................ ......................... 12 table 5 - 1 numicro m051 series pin description ................................ ................................ ........ 17 table 6 - 1 address space assignments for on - chip modules ................................ ...................... 24 table 6 - 2 watchdog timeout interval selection ................................ ................................ ............ 43 table 6 - 3 uart baud rate equation ................................ ................................ ............................ 45 table 6 - 4 uart baud rate setti ng table ................................ ................................ ..................... 46
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 6 - revision v 1.01 1 general description the numicro m05 1 ? ? ? ?
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 7 - revision v 1.01 2 features ? core ? arm ? cortex ? - m0 core runs up to 50 mhz. ? one 24 - bit system timer. ? supports low power sleep - mode. ? a s ingle - cycle 32 - bit hardware multiplier. ? nvic for the 32 interrupt inputs, each with 4 - levels of priority. ? supports serial wire debug ( swd) interface and 2 watchpoints/4 breakpoints. ? b uilt - in ldo for wide operating voltage range: 2. 5 v to 5.5v ? m emory ? 8k b /16k b flash memory for program memory (aprom) ? 4k b flash memory for data memory (dataflash) ? 4k b flash memory for loader (ldrom) ? 4 k b sram fo r internal scratch - pad ram (sram) ? clock control ? programmable system clock source ? 4~ 24 mhz e xternal crystal input ? 22 .1184 mhz internal oscillator ( trimmed to 3 % accuracy ) ? 10 khz l ow - power oscillator for w atchdog timer and wake - up in sleep mode ? pll allows c pu operation up to the maximum 50mhz ? i/ o port ? up to 4 0 g eneral - purpose i/o (gpio) pins for lqfp - 48 package ? four i/o modes: ? quasi bi - direction ? push - pull output ? open - drain output
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 8 - revision v 1.01 ? input only with high impendence ? ttl/schmitt trigger input selectable ? i/o pin ca n be configured as interrupt source with edge/level setting ? s upport s h igh driver and high sink io mode ? timer ? provides four channel 32 - bit timers, o ne 8 - bit pre - scale counter with 24 - bit up - timer for each timer. ? independent clock source for each timer. ? 24 - b it timer value is readable through tdr (timer data register) ? provides one - shot, periodic and toggle operation modes. ? provide event counter function. ? provide external capture /reset counter function equivalent to 8051 timer2. ? watch dog timer ? multiple clock so urces ? supports wake up from power down or sleep mode ? interrupt or reset selectable on watchdog time - out ? pwm ? built - in up to four 16 - bit pwm generators ; provid ing eight pwm outputs or four complementary paired pwm outputs ? individual clock source , clock divid er, 8 - bit pre - scalar and dead - zone generator for each pwm generator ? pwm interrupt synchronized to pwm period ? 16 - bit digital capture timers (shared with pwm timers) with rising/falling capture inputs ? supports capture interrupt ? uart ? up to two sets of uart de vice ? programmable baud - rate generator ? buffered receiver and transmitter, each with 1 5 byte s fifo
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 9 - revision v 1.01 ? optional f low control function (c ts and rts) ? supports irda (sir) function ? supports rs485 function ? supports lin function ? spi ? up to two sets of spi device. ? suppo rt s master/slave mode ? full duplex synchronous serial data transfer ? provide 3 wire function ? variable length of transfer data from 1 to 32 bits ? msb or lsb first data transfer ? rx latching data can be either at rising edge or at falling edge of serial clock ? tx sending data can be either at rising edge or at falling edge of serial clock ? supports byte suspend mode in 32 - bit transmission ? i 2 c ? supports m aster /s lave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master). ? a rbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handsh ake mechanism to suspend and resume serial transfer. ? programmable clocks allow versatile rate control. ? s upport s multiple address recognition ( four slave address with mask option) ? adc ? 12 - bit sar adc with 76 0k sps
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 10 - revision v 1.01 ? up to 8 - ch single - end ed input or 4 - ch diffe rential input ? s u pports single mode/burst mode/single - cycle scan mode/ continuo u s scan mode ? supports 2 ? compl ement /un - signed format in differential mode conversion result ? each channel with an individual result register ? support s conversion value monitoring ( or comparison) for threshold voltage detection ? conversion can be started either by software trigger or external pin trigger ? analog comparator ? up to 2 comparator analog modules ? e xternal input or internal band gap voltage selectable at negative node ? interrup t when compare result change ? power down wake up ? ebi (external bus interface) for external memory - mapped device access ? accessible space: 64kb in 8 - bit mode or 128kb in 16 - bit mode ? supports 8 - bit/16 - bit data width ? supports byte - write in 16 - bit data width ? in - system programming (isp) and in - circuit programming (icp) ? one built - in t emperature sensor with 1 resolutio n ? brown - o ut d etector ? with 4 levels: 4. 3 v/3. 7 v/2.7v/2.2v ? support s brown - o ut i nterrupt and r eset option ? 96 - bit unique id ? lvr ( low voltage reset ) ? threshold voltage levels: 2.0 v ? operating temperature: - 40 ~85 ? packages: ? green package (rohs) ? 48 - pin l qfp , 33 - pin qfn
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 11 - revision v 1.01 3 block diagram figure 3 - 1 numicro ? m051 series block diagram c o r t e x - m 0 5 0 m h z c l k _ c t l g p i o p 0 ~ p 4 a d c w a t c h d o g t i m e r i 2 c s p i 0 / 1 u a r t 0 / 1 p w m 0 ~ 7 t i m e r 0 / 1 1 0 k o s c p l l 2 2 m o s c e x t . 4 ~ 2 4 m x t a l l d o 2 . 5 ~ 5 . 5 v a d c 8 c h / 1 2 b i t s a r a d c 7 6 0 k s p s t i m e r 2 / 3 e b i a d [ 1 5 : 0 ] n c s n r d n w r m c l k a l e p a d c o n t r o l p o r b o d l v r 1 6 k b ( m 0 5 4 ) 8 k b ( m 0 5 2 ) a p r o m l d r o m i s p 4 k b c o n f i g d a t a f l a s h 4 k b s r a m 4 k b a n a l o g c o m p a r a t o r n w r h n w r l
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 12 - revision v 1.01 4 selection table numicro m051? series selection guide part number aprom ram data flash ldrom i/o ti mer connectivity comp pwm adc ebi isp icp package uart spi i2c m052lbn 8kb 4kb 4kb 4kb 40 4x32 - bit 2 2 1 2 8 8x12 - bit v v lqfp48 m052zbn 8kb 4kb 4kb 4kb 24 4x32 - bit 2 1 1 2 5 8x12 - bit v qfn33 m054lbn 16kb 4kb 4kb 4kb 40 4x32 - bit 2 2 1 2 8 8x12 - bit v v lqfp48 m054zbn 16kb 4kb 4kb 4kb 24 4x32 - bit 2 1 1 2 5 8x12 - bit v qfn33 table 4 - 1 numicro ? m051 series product selection guide figure 4 - 1 numicro ? naming rule m 0 5 x - x x x a r m c o r t e x m 0 l : l q f p 4 8 z : q f n 3 3 5 2 : 8 k f l a s h r o m 5 4 : 1 6 k f l a s h r o m n : - 4 0 ~ + 8 5 e : - 4 0 ~ + 1 0 5 c : - 4 0 ~ + 1 2 5 m 0 - x x x c p u c o r e 5 2 : 8 k f l a s h r o m 5 4 : 1 6 k f l a s h r o m n : - 4 0 ~ + 8 5 e : - 4 0 ~ + 1 0 5 c : - 4 0 ~ + 1 2 5 r e s e r v e d p a r t n u m b e r t e m p e r a t u r e p a c k a g e
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 13 - revision v 1.01 5 pin configuration 5.1 qfn 3 3 pin figure 5 - 1 numicro ? m051 series qfn33 pin di agram c p p 0 , a i n 5 , p 1 . 5 a v s s c p n 1 , r x d , p 3 . 0 c p p 1 , t x d , p 3 . 1 s d a , t 0 , p 3 . 4 s c l , t 1 , p 3 . 5 x t a l 2 x t a l 1 v s s l d o _ c a p p 2 . 2 , p w m 2 p 2 . 3 , p w m 3 p 2 . 4 , p w m 4 p 3 . 6 , c k o , c p o 0 p 0 . 7 , s c l k 1 p 4 . 6 , i c e _ c l k p 0 . 6 , m i s o _ 1 p 0 . 5 , m o s i _ 1 p 0 . 4 , s p i s s 1 p 2 . 5 , p w m 5 p 2 . 6 , p w m 6 , c p o 1 p 4 . 7 , i c e _ d a t t x d 1 , a i n 3 , p 1 . 3 r x d 1 , a i n 2 , p 1 . 2 c p n 0 , a i n 4 , p 1 . 4 a i n 0 , t 2 , p 1 . 0 t x d 1 , c t s 1 , p 0 . 0 a v d d r x d 1 , r t s 1 , p 0 . 1 v d d 3 3 v s s 3 2 1 2 4 r s t q f n 3 3 - p i n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 0 9 1 1 1 2 1 3 1 4 1 5 1 6 2 3 4 5 6 7 8 t o p t r a n s p a r e n t v i e w t 0 e x , s t a d c , i n t 0 , p 3 . 2
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 14 - revision v 1.01 5.2 lqfp 48 pin figure 5 - 2 numicro ? m051 series lqfp - 48 pin diagram 2 4 4 1 4 3 6 5 8 7 1 0 9 1 1 4 8 4 2 4 1 4 0 3 9 3 8 3 7 3 2 3 3 3 0 3 1 2 8 2 9 2 6 2 7 2 5 1 3 1 4 1 5 1 6 1 8 1 9 2 0 2 1 2 2 1 2 1 7 2 3 2 4 3 4 3 5 3 6 4 6 4 7 4 3 4 5 p w m 3 , p 4 . 3 p 4 . 0 , p w m 0 , t 2 e x 4 8 - p i n l q f p p w m 2 , p 4 . 2 m i s o _ 0 , a i n 6 , p 1 . 6 c p p 0 , m o s i _ 0 , a i n 5 , p 1 . 5 r s t s p i c l k 0 , a i n 7 , p 1 . 7 a v s s c p n 1 , r x d , p 3 . 0 c p p 1 , t x d , p 3 . 1 s d a , t 0 , p 3 . 4 s c l , t 1 , p 3 . 5 t 0 e x , s t a d c , i n t 0 , p 3 . 2 t 1 e x , m c l k , i n t 1 , p 3 . 3 x t a l 2 x t a l 1 v s s p 2 . 1 , a d 9 , p w m 1 l d o _ c a p p 2 . 2 , a d 1 0 , p w m 2 p 2 . 3 , a d 1 1 , p w m 3 p 2 . 4 , a d 1 2 , p w m 4 p 2 . 0 , a d 8 , p w m 0 p 3 . 7 , r d p 3 . 6 , w r , c k o , c p o 0 p 4 . 5 , a l e p 0 . 7 , a d 7 , s p i c l k 1 p 4 . 6 , i c e _ c l k p 0 . 6 , a d 6 , m i s o _ 1 p 0 . 5 , a d 5 , m o s i _ 1 p 0 . 4 , a d 4 , s p i s s 1 p 2 . 5 , a d 1 3 , p w m 5 p 2 . 6 , a d 1 4 , p w m 6 , c p o 1 p 2 . 7 , a d 1 5 , p w m 7 p 4 . 4 , / c s p 4 . 7 , i c e _ d a t p 4 . 1 , p w m 1 , t 3 e x t x d 1 , a i n 3 , p 1 . 3 r x d 1 , a i n 2 , p 1 . 2 c p n 0 , s p i s s 0 , a i n 4 , p 1 . 4 n w r h , t 3 , a i n 1 , p 1 . 1 n w r l , t 2 , a i n 0 , p 1 . 0 t x d 1 , c t s 1 , a d 0 , p 0 . 0 a v d d r x d 1 , r t s 1 , a d 1 , p 0 . 1 t x d , c t s 0 , a d 2 , p 0 . 2 r x d , r t s 0 , a d 3 , p 0 . 3 v d d
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 15 - revision v 1.01 5.3 pin description pin number symbol alternate function type [1] description qfn33 lqfp 48 1 2 3 11 16 xtal1 i (st) crystal1: this is the input pin to the internal inverting amplifier. the system clock is from external crystal or resonator when fosc[1:0] (config3[1:0]) are both logic 1 by default. 10 15 xtal2 o crystal2: this is the ou tput pin from the internal inverting amplifier. it emits the inverted signal of xtal1. 27 41 v dd p power supply: p ower supply to i/o ports and ldo source for internal pll and digital circuit . 12 17 v ss p ground: digital ground potential. 33 28 42 a v dd p power supply: p ower supply to internal analog circuit . 4 6 a v ss p ground: analog ground potential. 13 18 ldo_cap p ldo: ldo output pin note: it needs to be connected with a 1uf capacitor. 2 4 i (st) rese t: / rst pin is a schmitt trigger input pin for hardware device reset. a low on this pin for 768 clock counter of internal rc 22m while the system clock is running will reset the device. / rst pin has an internal pull - up resistor allowing power - on reset by simply connecting an external capacitor to gnd . 26 40 p0.0 cts1 ad0 txd1 [2] d, i/o port0: port 0 is an 8 - bit four mode output pin and two mode input. its multifunction pins are for cts1, rts1, cts0, rts0, spiss1, mosi _1 , miso _1 , and sp i clk 1 . p0 has an al ternative function as ad[7:0] while external memory accessing. during the external memory access, p0 will output high will be internal strong pulled - up rather than weak pull - up in order to drive out high byte address for external devices. these pins which are spiss1, mosi _1 , miso _1 , and s pi clk 1 for the spi function used. 25 39 p0.1 rts1 ad1 rxd1 [2] d, i/o nc 38 p0.2 cts0 ad2 txd [ 2 ] d, i/o nc 37 p0.3 rts0 ad3 rxd [ 2 ] d, i/o 24 35 p0.4 spi ss1 ad4 d, rst
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 16 - revision v 1.01 pin number symbol alternate function type [1] description qfn33 lqfp 48 1 2 3 i/o cts0/1: clear to send input pin for uart0/1 rts0/1: request to send output pin for uart0/1 the rxd/txd pins are for uart0 function used. the rxd1/txd1 pins are for uart1 function used. 23 34 p0.5 mosi_1 ad5 d, i/o 22 33 p0.6 miso_1 ad6 d, i/o 21 32 p0.7 s pi clk1 ad7 d, i/o 29 43 p1.0 t2 ain0 i/o port1: port 1 is an 8 - bit four mode output pin and two mode input. its multifunction pins are for t2, t 3 , rxd1, txd1 , spiss0, mosi _0 , miso _0 , and s pi clk 0 . these pins which are spiss0, mosi _0 , miso _0 , and sclk 0 for the spi function used. these pins which are ain0~ain7for the 12 bits adc function used. the rxd1/txd1 pins are for uart1 function used. the / pins are for low/high byte write enable output in 16 - bit data width of ebi. the cpn0/cp p0 pins are for comparator0 negative/positive inputs. the t2/t3 pins are for timer2/3 external even counter input. nc 44 p1.1 t 3 ain1 i/o 30 45 p1.2 rxd1 [3] ain2 i/o 31 46 p1.3 txd1 [3] ain3 i/o 32 47 p1.4 spi ss0 ain4 cpn0 i /o 1 1 p1.5 mosi _0 ain5 cpp0 i/o nc 2 p1.6 miso _0 ain6 i/o nc 3 p1.7 s pi clk 0 ain7 i/o nc 19 p2.0 pwm0 [ 2 ] a d 8 d, i/o port2: port 2 is an 8 - bit four mode output pin and two mode input. it has an alternative function p 2 has an alternative function as ad[ 15 : 8 ] while external memory accessing. during the external memory access, p 2 will output high will be internal strong pulled - up rather than weak pull - up in order to drive out high byte address for external devices. these pins which are pwm0~pwm7 for the pwm function used in the lqfp48 package. the cpo1 pin is the output of comparator1. nc 20 p2.1 pwm1 [ 2 ] a d 9 d, i/o 14 21 p2.2 pwm2 [ 2 ] a d 10 d, i/o 15 22 p2.3 pwm3 [ 2 ] a d 11 d, i/o 16 23 p2.4 pwm4 [ 2 ] a d 12 d, i/o 17 25 p2.5 pwm5 [ 2 ] a d 13 d, i/o wrl wrl wrh wrh
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 17 - revision v 1.01 pin number symbol alternate function type [1] description qfn33 lqfp 48 1 2 3 18 26 p2.6 pwm6 [ 2 ] a d 14 cpo1 d, i/o nc 27 p2.7 pwm7 [ 2 ] a d 15 d, i/o 3 5 p3.0 rxd [ 2 ] cpn1 i/o port3: port 3 is an 8 - bit four mode output pin and two mode input. its multifunction pins are for rxd, txd, , , t0, t1, , and . the rxd/txd pins are for uart0 function used. the sda/sck pins are for i 2 c function used. mclk: ebi clock output pin. cko: hclk clock output the stadc pin is for adc external trigger input. the cpn1/cpp1 pins are for comparator1 negative/positive inputs. the cpo0 pin is the output of comparator0. the t0/t1 pins are for timer0/1 external even counter input. the t0ex/t1ex pins are for external capture/reset trigger input of timer0/1. 5 7 p3.1 txd [ 2 ] cpp1 i/o 6 8 p3.2 stadc t0ex i/o nc 9 p3.3 mclk t1ex i/o 7 10 p3.4 t0 sda i/o 8 11 p3.5 t1 scl i/o 9 13 p3.6 cko c p o 0 i/o nc 14 p3.7 i/o nc 24 p4.0 pwm0 [2 ] t2ex i/o port4: port 4 is an 8 - bit four mode output pin and two mode input. its multifunction pins are for /cs, ale, ice_clk and ice_dat . for ebi (external bus interface) used. ale (address latch enable) is used to ena ble the address latch that separates the address from the data on port 0 and port 2 . the ice_clk/ice_dat pins are for jtag - ice function used. pwm0 - 3 can be used from p4.0 - p4.3 when ebi is active. the t2ex/t3ex pins are for external capture/reset trigger in put of timer2/3. nc 3 6 p4.1 pwm1 [2 ] t3ex i/o nc 4 8 p4.2 pwm2 [2 ] i/o nc 12 p4.3 pwm3 [2 ] i/o nc 28 p4.4 i/o nc 29 p4.5 ale i/o 19 30 p 4.6 ice_clk i/o 20 31 p 4.7 ice_dat i/o table 5 - 1 numicro ? m051 series pin description [1] i /o type description. i: input, o: output, i/o: quasi bi - direction, d: open - drain, p: power pins, 0 int 1 int wr rd wr cs
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 18 - revision v 1.01 st: schmitt trigger. [2] the pins features which are set by s/w. only one - set pin can be used while s/w to set it.
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 19 - revision v 1.01 6 functional descripti on 6.1 arm? cortex? - m0 c ore the cortex ? - m0 processor is a configurable, multistage, 32 - bit risc processor. it has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functio nality. the processor can execute thumb code and is compatible with other cortex - m profile processor. the profile supports two modes - thread and handler modes. handler mode is entered as a result of an exception. an exception return can only be issued in h andler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 6 - 1 shows the functional controller of processor. figure 6 - 1 functional block diagram the implemented device provides: a low gate count processor t he features: ? the armv6 - m thumb ? instruction set. ? thumb - 2 technology. ? armv6 - m compliant 24 - bit systick timer. ? a 32 - bit hardware multiplier. ? the syste m interface supports little - endian data accesses. ? the ability to have deterministic, fixed - latency, interrupt handling. ? load/store - multiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling. c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 20 - revision v 1.01 ? c application binary interface compliant exception model. this is the armv6 - m, c application binary interface(c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers. ? low power sleep - mode entry using wait for interrupt (wfi), wa it for even t (wfe) instructions, or the return from interrupt sleep - on - exit feature. nvic features: ? 32 external interrupt inputs, each with four levels of priority. ? dedicated non - maskable interrupt (nmi) input. ? support for both level - sensitive and pulse - s ensitive interrupt lines ? wake - up interrupt controller (wic), support s ultra - low power sleep mode . debug support : ? four hardware breakpoints. ? two watchpoints. ? program counter sampling register (pcsr) for non - intrusive code profiling. ? single step and vector catch capabilities. bus interfaces: ? single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory. ? single 32 - bit slave port that supports the dap (debug access port).
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 21 - revision v 1.01 6.2 system manager 6.2.1 overview the foll owing functions are included in system manager section ? system resets ? system memory map ? system management registers for part number id , chip reset and on - chip module reset , multi - function al pin control ? system timer (systick) ? nested vectored interrupt contr oller (nvic) ? system control registers 6.2.2 system reset the system reset includes one of the list below event occurs. for these reset event flags can be read by rst s rc register. ? the power - on reset (por) ? the low level on the /reset pin ? watchdog time out reset (wdt) ? low voltage reset (lvr) ? brown - out detected reset (bod) ? cpu reset ? software one shot reset
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 22 - revision v 1.01 6.2.3 system power architecture in this device, the power architecture is divided into three segments. ? a nalog power from a v dd and a v ss provides the power for analog module operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. the output s of internal voltage regulator , which is ldo, require an external capacitor which should be located close to the corresponding pin. the figure 6 - 2 shows the power architecture of this device. figure 6 - 2 numicro m05 1 ? series power ar chitecture diagram 5 v t o 1 . 8 v l d o p l l 1 2 - b i t s a r - a d c b r o w n o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s l d o 1 u f i o c e l l p 0 - p 4 p v s s m 0 5 1 s e r i e s p o w e r d i s t r i b u t i o n
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 23 - revision v 1.01 6.2.4 whole system memory map numicro m05 1 ? series provides a 4g - byte address space. the memory locations assigned to each on - chip modules are shown in table 6 - 1 . the detailed register memory address ing and programming will be described in the following sections for 1 individual on - chip peripherals . numicro m05 1 ? series only supports little - endian data format. address space token modules flash & sram memory space 0x0000_0000 C 0x000 0 _ffff flash_ba f lash memory space ( 64 kb) 0x2000_0000 C 0x2000_ 0f ff sram_ba sram memory space ( 4 kb) ebi space (0x 6 000_0000 ~ 0x 6 00 1 _ f fff) 0x 6 000_ 0 000 C 0x 6 00 1 _ f fff ebi _ba external memory space (128kb) ahb modules space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000 _01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio (p0~p4) control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x500 1 _ 0 000 C 0x500 1 _ 03 ff ebi_ctl _ba ebi control registers (128kb) apb modules space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watch - dog timer control registers 0x4001_0000 C 0x400 1_3fff tmr0 1 _ba timer0 /timer1 control registers 0x4002_0000 C 0x4002_3fff i2c_ba i 2 c interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi 1 _ba spi 1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwm a _ba pwm0 /1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x400d_0000 C 0x400d_3fff acmp_ba analog comparator control registers
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 24 - revision v 1.01 address space token modules 0x400e_0000 C 0x400e_ffff adc_b a analog - digital - converter (adc) control registers 0x4011_0000 C 0x4011_3fff tmr2 3 _ba timer2 /timer3 control registers 0x40 1 4_0000 C 0x40 1 4_3fff pwm b _ba pwm 4/5/6/7 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers system contr ol space (0x e000 _ e 000 ~ 0x e000 _ e fff) 0x e000 _ e 0 1 0 C 0x e000 _ e0 ff scs_ba system timer control registers 0x e000 _ e10 0 C 0x e000 _ ec ff scs_ba external interrupt controller control registers 0x e000 _ ed0 0 C 0x e000 _ ed8 f scs_ba system control registers table 6 - 1 address space assignments for on - chip modules
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 25 - revision v 1.01 6.2.5 whole system memory mapping table 6.2.6 system timer (systick) the cortex - m0 includes an integrated system timer, systick. systick provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current value m052/54/58/516 4 gb 0xffff_ffff | system control 0xe000_f000 system timer control 0xe000_e000 scs_ba 0xe000_efff 0xe000_e000 0xe000_e00f | 0x6002_0000 0x6001_ffff 0x6000_0000 0x5fff_ffff | 0x5020_0000 ahb peripherals 0x501f_ffff ebi control 0x5001_0000 ebi_ctl_ba 0x5000_0000 fmc 0x5000_c000 flash_ba 0x4fff_ffff gpio control 0x5000_4000 gpio_ba interrupt multiplexer control 0x5000_0300 int_ba clock control 0x5000_0200 clk_ba 0x4020_0000 system global control 0x5000_0000 gcr_ba 0x401f_ffff 1 gb 0x4000_0000 0x3fff_ffff apb peripherals uart1 control 0x4015_0000 uart1_ba 0x2000_1000 pwm4/5/6/7 control 0x4014_0000 pwmb_ba 0x2000_0fff timer2/timer3 control 0x4011_0000 tmr23_ba adc control 0x400e_0000 adc_ba comp control 0x400d_0000 acmp_ba uart0 control 0x4005_0000 uart0_ba 0.5 gb 0x2000_0000 pwm0/1/2/3 control 0x4004_0000 pwma_ba 0x1fff_ffff spi1 control 0x4003_4000 spi1_ba spi0 control 0x4003_0000 spi0_ba i2c control 0x4002_0000 i2c_ba 0x0001_0000 timer0/timer1 control 0x4001_0000 tmr01_ba 64 kb on-chip flash (m0516) 0x0000_ffff wdt control 0x4000_4000 wdt_ba 32 kb on-chip flash (m058) 0x0000_7fff 16 kb on-chip flash (m054) 0x0000_3fff 0x0000_1fff 0 gb 0x0000_0000 | | apb 8 kb on-chip flash (m052) reserved reserved | | 4 kb sram (m052/m054/m058/m0516) reserved ahb reserved | system control reserved reserved ebi
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 26 - revision v 1.01 register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock edge, then decrement on subsequent clocks. when the counter transitions to zero, the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an a rbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the documents arm? cortex? - m0 technical reference manual and arm? v6 - m architecture reference manual.
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 27 - revision v 1.01 6.2.7 nested vectored interrupt controller (nvic) cortex - m0 provides an interrupt controller as an integral part of t he exception mode, named as nested vectored interrupt controller (nvic). it is closely coupled to the processor kernel and provides following features: ? nested and vectored interrupt support ? automatic processor state saving and restoration ? dynamic priorit y changing ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. al l of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running one?s priority. if the priority of the new interr upt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to dete rmine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back i nterrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capabilit y. for more detailed information, please refer to the documents arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 28 - revision v 1.01 6.3 clock controller 6.3.1 overview the clock controller generates the clock s for the whole chip , includ in g system clocks and all peripheral clocks . the clock controller also implements the power control function with the individually clock on/off control, clock source select ion and clock divider . the chip will not enter power - d ow n mode until cpu set s the p owe r d own enable bit (pwr_down _en ) and cortex - m0 core execute s the wfi i nstruction. after that, chip enter power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. i n the power down mode, the clock controller turn s off the ext ernal crystal and internal 22 .1184 mhz oscillator to reduce the overall system power consumption. 6.3.2 clock generator block diagram the clock generator consists of 4 sources which list below: ? one external 4~24 mhz crystal ? one internal 22.1184 m hz rc oscillator ? one programmable pll fout(pll source consists of external 4~24 mhz crystal and internal 22.1184m ) ? one internal 10 k hz oscillator
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 29 - revision v 1.01 figure 6 - 3 clock generator block diagram 1 0 p l l c o n [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 1 2 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z r e s e r v e d 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 3 a d c u a r t 0 - 2 a c m p i 2 c s p i 0 - 1 f d i v p w m 0 - 1 w d t p w m 2 - 3 p w m 4 - 5 p w m 6 - 7 t m r 0 t m r 1 t m r 2 c p u f m c e b i 1 0 k h z 1 1 1 0 1 0 0 0 1 0 0 0 h c l k r e s e r v e d 4 ~ 2 4 m h z 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t r e s e r v e d 4 ~ 2 4 m h z 1 0 k h z 2 2 . 1 1 8 4 m h z 0 0 0 c l k s e l 0 [ 2 : 0 ] s y s t _ c s r [ 2 ] c p u c l k 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 1 [ 3 : 2 ] 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] 1 1 1 0 0 1 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z r e s e r v e d c l k s e l 2 [ 7 : 2 ] c l k s e l 1 [ 3 1 : 2 8 ] 2 2 . 1 1 8 4 m h z b o d 1 0 k h z 1 / ( a d c _ n + 1 ) 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t _ n + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 0 1 r e s e r v e d 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 5 : 2 4 ] 2 2 . 1 1 8 4 m h z 1 0
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 30 - revision v 1.01 6.3.3 syst em clock & systick clock the system clock has 4 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_s(clksel0[2:0]). the block diagram is shown in the figure 6 - 4 . figure 6 - 4 system clock block diagram the clock source of systick in cortex - m0 core can use cpu clock or external clock (syst_csr[2]). i f using external clock, the systick cloc k ( s tclk) has 4 clock sources. the clock source switch depends on the setting of the register stclk_ s ( clksel0[5:3]. the block diagram is shown in the figure 6 - 5 . figure 6 - 5 systick clock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t r e s e r v e d 4 ~ 2 4 m h z 1 0 k h z h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k 1 1 1 0 1 0 h c l k 4 ~ 2 4 m h z s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 1 1 / 2 1 / 2 4 ~ 2 4 m h z 0 1 1 1 / 2 0 0 0 r e s e r v e d
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 31 - revision v 1.01 6.3.4 ahb clock source select figure 6 - 6 ahb clock source for hclk i s p _ e n ( a h b c l k [ 2 ] ) h c l k i s p e b i _ e n ( a h b c l k [ 3 ] ) h c l k e b i
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 32 - revision v 1.01 6.3.5 peripherals clock source select the peripherals clock had d ifferent clock source switch setting which depends on the different peripheral. figure 6 - 7 peripherals clock source select for pclk w d t _ e n ( a p b c l k [ 0 ] ) p c l k w a t c h d o g t i m e r t i m e r 1 t i m e r 0 t m r 0 _ e n ( a p b c l k [ 2 ] ) t m r 1 _ e n ( a p b c l k [ 3 ] ) t i m e r 2 t m r 2 _ e n ( a p b c l k [ 4 ] ) t i m e r 3 t m r 3 _ e n ( a p b c l k [ 5 ] ) f r e q u e n c y d i v i d e r f d i v _ e n ( a p b c l k [ 6 ] ) i 2 c i 2 c _ e n ( a p b c l k 1 [ 8 ] ) s p i 0 s p i 0 _ e n ( a p b c l k [ 1 2 ] ) s p i 1 s p i 1 _ e n ( a p b c l k [ 1 3 ] ) u a r t 0 u a r t 0 _ e n ( a p b c l k [ 1 6 ] ) u a r t 1 u a r t 1 _ e n ( a p b c l k [ 1 7 ] ) p w m 0 1 p w m 0 1 _ e n ( a p b c l k [ 2 0 ] ) p w m 2 3 p w m 2 3 _ e n ( a p b c l k [ 2 1 ] ) p w m 4 5 p w m 4 5 _ e n ( a p b c l k [ 2 2 ] ) p w m 6 7 p w m 6 7 _ e n ( a p b c l k [ 2 3 ] ) a d c a c m p a d c _ e n ( a p b c l k [ 2 8 ] ) a c m p _ e n ( a p b c l k [ 3 0 ] )
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 33 - revision v 1.01 6.3.6 power d own m ode (deep sleep mode) clock whe n chip enter into power down mode, most of clock sources , peripheral clock s and system clock will be disable d directly . internal 10khz could be still active in power down /deep power down mode if cpu does not disable it before entering power down mode. ip e ngine clock could be still active in power down /deep power down mode if ip adopts i nternal 10khz does not be disabled respectively. 6.3.7 frequency divider output this device is equipped a power - of - 2 frequency divider which is composed by 16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to p3.6 . therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 17 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in freqdiv.fsel[3:0]. when write 1 to divider_en (frqdiv[4]), the chained counter sta rts to count. when write 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. figure 6 - 8 clock source of frequency divider 1 1 1 0 0 1 0 0 h c l k r e s e r v e d 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 34 - revision v 1.01 figure 6 - 9 block diagram of frequency divider 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c l k o f r q d i v _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 35 - revision v 1.01 6.4 general purpose i/o 6.4.1 overview there are 40 general purpose i/o pins shared with special feature functions in t his mcu. the 40 pins are arranged in 5 ports named with p0, p1, p2, p3 and p4. each port equips maximum 8 pins. each one of the 40 pins is independent and has the corresponding register bits to control the pin mode function and data the i/o type of each o f i/o pins can be software configured individually as input, output, open - drain or quasi - bidirectional mode. the all pins of i/o type stay in quasi - bidirectional mode and port data register px_dout[7:0] resets to 0x000_00ff. each i/o pin equips a very weak ly individual pull - up resistor which is about 110k ? ~300k ? for v dd is from 5.0v to 2.5v. 6.4.1.1 input mode explanation set px_pmd (pmdn[1:0]) to 00b the px[n] pin is in input mode and the i/o pin is in tri - state(high impedance) without output drive capability . the px_pin value reflects the status of the corresponding port pins. 6.4.1.2 output mode explanation set px_pmd (pmdn[1:0]) to 2?b01 the px[n] pin is in output mode and the i/o pin supports digital output function with source/sink current capability. the bit value in t he corresponding bit [n] of px_dout is driven on the pin. figure 6 - 10 push - pull output port pin input data port latch data p n vdd
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 36 - revision v 1.01 6.4.1.3 open - drain mode explanation set px_pmd (pmdn[1:0]) to 2?b10 the px[n] pin is in open - drain mode and the i/o pin supports digital output function but only with sink current capability, an additional pull - up resister is needed for driving high state. if the bit value in the corresponding bit [n] of px_dout is 0, the pin drive a low output on the pin. if the bit value in the corresponding bit [n] of px_dout is 1, the pin output drives high that is controlled by the internal pull - up resistor or the external pull high resistor. figure 6 - 11 open - drain output 6.4.1.4 quasi - bidirectional mode explanation set px_pmd (pmdn[1:0]) to 2?b11 the px[n] pin is in quasi - bidirectional mode and the i/o pin supports digital output and input function at the same time but the source current is only up to hundreds ua. before the digital input function is performed the corresponding bit in px_dout must be set to 1. t he quasi - bidirectional output is common on the 80c51 and most of its derivatives. if the bit value in the corresponding bit [n] of p x_dout is 0, the pin drive a low output on the pin. if the bit value in the corresponding bit [n] of px_dout is 1, the pin will check the pin value. if pin value is high, no action takes. if pin state is low, then pin will drive strong high with 2 c lock cycles on the pin and then disable the strong output drive and then the pin status is control by internal pull - up resistor. note that the source current capability in quasi - bidirectional mode is only about 200ua to 30ua for v dd is form 5.0v to 2.5v figure 6 - 12 quasi - bidirectional i/o mode port pin port latch data n input data port pin 2 cpu clock delay input data port latch data p p p n vdd strong very weak weak
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 37 - revision v 1.01 6.5 i 2 c serial interface controller (master/slave) 6.5.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient m ethod of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte - by - byte basis. each data byte is 8 bits long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the figure 6 - 13 for more detail i 2 c bus timing. figure 6 - 13 i 2 c bus timing the device?s on - chip i 2 c provides the serial interfac e that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda (serial data line) and scl (ser ial clock line). pull up resistor is needed on pin sda and scl for i 2 c operation as these are open drain pins. when the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. t buf stop sda scl start t hd ; sta t low t hd ; dat t high t f t su ; dat repeated start t su ; sta t su ; sto stop t r
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 38 - revision v 1.01 6.5.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? support master and slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously tr ansmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume s erial transfer ? built - in a 14 - bit time - out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? external pull - up are needed for high output ? programmable clocks allow versatile rate control ? supports 7 - bit addressin g mode ? i 2 c - bus controllers support multiple address recognition ( four slave address with mask option)
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 39 - revision v 1.01 6.6 pwm generator and capture timer 6.6.1 overview numicro m05 1 ? series ha s 2 sets of pwm group supports 4 sets of pwm generators which can be configured as 8 i ndependent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable dead - zone generators. each pwm generator has one 8 - bit prescaler, one clock divider with 5 divided frequencie s (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm down - counters for pwm period control, two 16 - bit comparators for pwm duty control and one dead - zone generator. the 4 sets of pwm generators provide eight independent p wm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one - shot m ode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm timing, period, duty and dead - time are determined by pwm0 time r and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead - zone generator 2, 4 and 6, respectively. refer to figures bellowed for the architecture of pwm timers. when the 16 - bit period down counter reaches zero, the interrupt request is generated. if pwm - timer is set as auto - reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically then start decr easing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capt ure0 and pwm0 share one timer which is included in pwm 0; and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer before enable capture feature. after capture feature is enabled, the capture always latched pwm - counter t o capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel has a falling transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ ie0[1] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capture channel 0 to chann el 3 on each group have the same feature by setting the corresponding control bits in ccr 0 and ccr 2 . for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm c an capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, they are: read pi i r to get interrupt source and read pwm_crlx/pwm_cflx(x=0 and 3 ) to get capture value and finally write 1 to c lear pi i r. if interrupt latency will take time t0 to finish, the capture signal mustn?t transition during this interval (t0) . in this case, the maximum capture frequency will be
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 40 - revision v 1.01 1/t0. for example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 n s so the maximum capture frequency will is 1/900ns 1000 k hz 6.6.2 features 6.6.2.1 pwm function features: pwm group has two pwm generators. each pwm generator supports one 8 - bit prescaler, one clock divider, two pwm - timers (down counter), one dead - zone generator and two pwm outputs. ? up to 16 bits resolution ? pwm interrupt request synchronized with pwm period ? one - shot or auto - reload mode pwm ? up to 2 pwm group (pwma/pwmb) to support 8 pwm channels 6.6.2.2 capture function features: ? timing control logic shared with pwm generators ? 8 c apture input channels shared with 8 pwm output channels ? each channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 41 - revision v 1.01 6.7 serial peripheral interface (spi) 6.7.1 overview the serial peripheral inter face ( spi ) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4 - wire bi - direction interface. numicro m05 1 ? series contains up to two sets of spi controller perform ing a seri al - to - parallel conversion on data received from a peripheral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be set as a master, i t also can be configured as a slave device controlled b y an off - chip master device. this controller supports a variable serial clock for special application. 6.7.2 features ? up to two sets of spi controller ? support master or slave mode operation ? configurable bit length up to 32 - bit of a transfer word and configurable word numbers up to 2 of a transaction, so the maximum bit length is 64 - bit for each data transfer ? provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer ? support msb or lsb first transfer ? support byte reorder function ? support byte or word suspend mode ? support two programmable serial clock frequencies in master mode ? support three wire, no slave select signal, bi - direction interface ? the spi clock rate can be configured to equal the system clock rate
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 42 - revision v 1.01 6.8 timer controller 6.8.1 overview numicro m05 1 ? series timer controller includes four 32 - bit timers , which allow s user to easily implement a timer control for applications. the timer can perform functions like frequency measurement, event counting, interval mea surement, clock generation, delay timing, and so on. the timer can generates an interrupt signal upon timeout, or provide the current counting value during operation. 6.8.2 features : ? 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter ? in dependent clock source for each timer ? provides one - shot, periodic, toggle and continuous counting operation modes ? time out period = (period of timer clock input) * (8 - bit pre - scale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit timer value is readable through tdr (timer data register) ? support event counting function to count the event from external pin ? support input capture function to capture or reset counter value
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 43 - revision v 1.01 6.9 watchdog timer (wdt) 6.9.1 overview the purpose of watchdog timer is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports another function to wakeup chip from power down mode. the watchdog timer includes an 18 - bit free running counter with programmable time - out intervals. table 6 - 2 show the watchdog timeout interval selection and figure 6.9 - 1 shows the timing of watchdog interrupt signa l and reset signal. setting wte (wdtcr [7]) enables the watchdog timer and the wdt counter starts counting up. when the counter reaches the selected time - out interval, watchdog timer interrupt flag wtif will be set immediately to request a wdt interrupt if the watchdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time - out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to reset the 18 - bit wdt counter to avoid chip from watchdog t imer reset before the delay time expires. wtr bit is cleared automatically by hardware after wdt counter is reset. there are eight time - out intervals with specific delay time which are selected by watchdog timer interval select bits wtis (wdtcr [10:8]). if the wdt counter has not been cleared after the specific delay time expires, the watchdog timer will set watchdog timer reset flag (wtrf) high and reset chip. this reset will last 63 wdt clocks (t rst ) then chip restarts executing program from reset vector (0x0000 0000). wtrf will not be cleared by watchdog reset. user may poll wtfr by software to recognize the reset source. wdt also provides wakeup function. when chip is powered down and the watchdog timer wake - up function enable bit (wdtr[4]) is set, if th e wdt counter reaches the specific time interval defined by wtis (wdtcr [10:8]) , the chip is waken up from power down state. first example, if wtis is set as 000, the specific time interval for chip to wake up from power down state is 2 4 * t wdt . when powe r down command is set by software, then, chip enters power down state. after 2 4 * t wdt time is elapsed, chip is waken up from power down state. second example, if wtis (wdtcr [10:8]) is set as 111, the specific time interval for chip to wake up from power down state is 2 18 * t wdt . if power down command is set by software, then, chip enters power down state. after 2 18 * t wdt time is elapsed, chip is waken up from power down state. notice if wtre (wdtcr [1]) is set to 1, after chip is waken up, software shoul d chip the watchdog timer counter by setting wtr(wdtcr [0]) to 1 as soon as possible. otherwise, if the watchdog timer counter is not cleared by setting wtr (wdtcr [0]) to 1 before time starting from waking up to software clearing watchdog timer counter i s over 1024 * t wdt , the chip is reset by watchdog timer. wtis timeout interval selection t tis interrupt period t int wtr timeout interval (wdt_clk=10 khz) m in . t wtr ~ m ax . t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t w dt 1024 * t wdt 26.2144 s ~ 26.3168 s table 6 - 2 watchdog timeout interval selection
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 44 - revision v 1.01 figure 6 - 14 timing of interrupt and reset sig nal 6.9.2 features ? 18 - bit free running counter to avoid chip from watchdog timer reset before the delay time expires. ? selectable time - out interval (2 4 ~ 2 18 ) and the time out interval is 104 ms ~ 26.3168 s (if wdt_clk = 10 khz). ? reset period = (1 / 10 khz) * 63, if wdt_clk = 10 khz. t t i s r s t i n t 1 0 2 4 * t w d t 6 3 * t w d t m i n i m u m t w t r t i n t t r s t m a x i m u m t w t r t w d t x t w d t : w a t c h d o g e n g i n e c l o c k t i m e p e r i o d x t t i s : w a t c h d o g t i m e o u t i n t e r v a l s e l e c t i o n p e r i o d x t i n t : w a t c h d o g i n t e r r u p t p e r i o d x t r s t : w a t c h d o g r e s e t p e r i o d x t w t r : w a t c h d o g t i m e o u t i n t e r v a l p e r i o d
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 45 - revision v 1.01 6.10 uart interface controller (uart) numicro m05 1 ? series provides two channels of universal asynchronous receiver/transmitters (uart). uart 0 ~ 1 perform s normal speed uart, and support flow control function. 6.10.1 overview the universal asynch ronous receiver/transmitter (uart) performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function, lin master/slave mo de function and rs - 485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (parity error or framing error o r break interrupt) (int_rls), receiver buffer time out interrupt (int_tout), modem/wakeup status interrupt (int_modem), buffer error interrupt (int_buf_err) and lin receiver break field detected interrupt (int_lin_rx_break). the uart0 and uart1 are built - in with a 16 - byte tra nsmitter fifo (tx_fifo) and a 16 - byte receiver fifo (rx_fifo) that reduces the number of i nterrupts presented to the cpu . the cpu can read the status of the uart at any time during the operation. the reported status information include s the type and condition of the transfer operations being performed b y the uart, as well as 3 error conditions (parity error, framing error, break interrupt) probably occur while receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). table 6 - 3 lists the equations in the various conditions and table 6 - 4 list the uart baud rate setting table. mode div_x_en div_x_one divider x brd m baud rate equation 0 0 0 b a 16 uart_clk / [16 * (a+2)] 1 1 0 b a b +1 uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a 1 uart_clk / (a+2), a must >=3 table 6 - 3 uart baud rate equation
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 46 - revision v 1.01 system clock = 22.1184mhz baud rate mode0 mode1 mode2 921600 n ot suppor t a=0,b=11 a=22 460800 a=1 a=1,b=15 a=2,b=11 a=46 230400 a=4 a=4,b=15 a=6,b=11 a=94 115200 a=10 a=10,b=15 a=14,b=11 a=190 57600 a=22 a=22,b=15 a=30,b=11 a=382 38400 a=34 a=62,b=8 a=46,b=11 a=34,b=15 a=574 19200 a=70 a=126,b=8 a=94,b=11 a=70,b=15 a=11 50 9600 a=142 a=254,b=8 a=190,b=11 a=142,b=15 a=2302 4800 a=286 a=510,b=8 a=382,b=11 a=286,b=15 a=4606 table 6 - 4 uart baud rate setting table the uart0 and uart1 controllers support auto - flow control funct ion that uses two low - level signals, /cts (clear - to - send) and /rts (request - to - send), to control the flow of data transfer between the uart and external devices (ex: modem). when auto - flow is enabled, the uart is not allowed to receive data until the uart asserts /rts to external device. when the number of bytes in the rx fifo equals the value of rts_tri_lev (ua_fcr [19:16]), the /rts is de - asserted. the uart sends data out when uart controller detects /cts is ass erted from external device. if the vali d ass erted /cts is not detected , the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) function (user must set ua_fun_sel [1 :0 ] = ? 10 ? to enable irda function). the sir specification defines a short - ra nge infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half - duplex on ly. so it cannot transmit and receive data at the same time. the irda sir physical layer specifies a minimum 10ms transfer delay between transmission and reception. this delay feature must be implemented by software. the alternate function of uart controll ers is lin (local interconnect network) function. the lin mode is selected by setting ua_fun_sel [1:0] = ? 01 ? . in lin mode, one start bit and 8 - bit data format with 1 - bit stop bit are required in accordance with the lin standard.
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 47 - revision v 1.01 a nother alternate function of uart controllers is rs - 485 9 bit mode function, and direction control provided by rts pin or can program gpio (p 0.3 for rts0 and p 0.1 for rts1) to implement the function by software. the rs - 485 mode is selected by setting the ua_fun_sel register to se lect rs - 485 function. the rs - 485 driver control is implemented by using the rts control signal from an asynchronous serial port to enable the rs - 485 driver. in rs - 485 mode, many characteristics of the rx and tx are same as uart. 6.10.2 features ? full duplex, async hronous communications ? separate receive / transmit 16/16 bytes entry fifo for data payloads ? support hardware auto flow control/flow control function (cts, rts) and programmable rts flow control trigger level ? programmable receiver buffer trigger level ? supp ort programmable baud - rate generator for each channel individually ? support cts wake up function ? support 8 bit receiver buffer time out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting ua_ tor [dly] register ? support break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programmable serial - interface characteristics ? programmable number of data bit, 5, 6, 7, 8 bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation ? support irda sir function mode ? support for 3/16 bit duration for normal mode ? support lin function mode ? support lin master/slave mode ? s upport programmable break generation function for transmitter ? support break detect function for receiver ? support rs - 485 function mode. ? support rs - 485 9bit mode ? support hardware or software enable to program rts pin to control rs - 485 transmission direction direct ly
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 48 - revision v 1.01 6.11 analog - to - digital converter (adc) 6.11.1 overview numicro m05 1 ? series contain one 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter supports four operation modes: single, burst, sin gle - cycle scan and continuous scan mode. the a/d converters can be started by software and external stadc/p3.2 pin. 6.11.2 features ? analog input voltage range: 0~a v dd (max to 5.0v). ? 12 - bit resolution and 10 - bit accuracy is guaranteed. ? up to 8 single - end analog i nput channels or 4 differential analog input channels. ? maximum adc clock frequency is 16 mhz. ? up to 760 k sps conversion rate. ? four operating modes - single mode: a/d conversion is performed one time on a specified channel. - single - cycle scan mode: a/d conver sion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel. - continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion. - burst mode: a/d conversion will sample and convert the specified single channel and sequentially store in fifo . ? an a/d conversion can be started by - software write 1 to adst bit - external pin stadc ? conversion results are held in data registers for each chan nel with valid and overrun indicators. ? conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting. ? channel 7 supports 3 input sources: external analo g voltage , internal bandgap voltage , and internal temperature sensor output .
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 49 - revision v 1.01 6.12 external bus interface (ebi) 6.12.1 overview numicro m05 1 ? series equips an external bus interface (ebi) for external device used. to save the connections between external device and th is chip, ebi support address bus and data bus multiplex mode. and, address latch enable (ale) signal supported differentiate the address and data cycle. 6.12.2 features external bus interface has the following functions : 1. external devices with max. 64k - byte size ( 8 bit data width)/128k - byte (16 bit data width) supported 2. variable external bus base clock (mclk) supported 3. 8 bit or 16 bit data width supported 4. variable data access time (tacc), address latch enable time (tale) and address hold time (tahd) supported 5. addre ss bus and data bus multiplex mode supported to save the address pins 6. configurable idle cycle supported for different access condition: write command finish (w2x), read - to - read (r2r)
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 50 - revision v 1.01 6.13 flash memory controller (fmc) 6.13.1 overview numicro m05 1 ? series equips with 16k/8k bytes on chip embedded flash eeprom for application program memory (aprom) that can be updated through isp/iap procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on co rtex - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro m05 1 ? series also provide additional 4 k bytes data flash for user to store some application depended data before ch ip power off in 16/8 k bytes aprom m odel. 6.13.2 features ? run up to 50 mhz with zero wait state for continuous address read access ? 16/8kb application program memory (aprom) ? 4 k b in system programming (isp) loader program memory (ldrom) ? f ixed 4 k b data flash with 512 bytes page erase unit ? in system p rogram (isp)/in application program (iap) to update on chip flash eprom
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 51 - revision v 1.01 7 typical application circuit aa12 ri2c1 4.7k ad0 ri2c2 4.7k ad1 ad2 dvdd rxd0 txd0 dvdd i2c-eeprom 24lc64 ui2c1 soic8\1.27\5.6mm
gnd 4 a2 3 a1 2 a0 1 sda 5 scl 6 wp 7 vcc 8 i2c ad3 eeprom address:0h cb9 0.1 uf dvdd met22 met23 dvdd dvdd miso_1 nss1 p32 uspi1 w25x16vssig soic-8p cs# 1 do 2 wp# 3 gnd 4 di 5 clk 6 hold# 7 vcc 8 spi dvdd rspi1 4.7k rspi2 4.7k cb7 0.1 uf sclk1 mosi_1 sda scl sda ad4 scl nwr ad5 ad12 ad6 ad11 ad10 ad13 ad7 ad14 nticerst avdd ad5 ad6 p40 ale ad7 ad9 ad8 ad3 uart_txd rxd0 txd1 rxd1 txd0 s1 sw dip-4 swdip8 1 2 3 4 8 7 6 5 uart_rxd ad4 nrd ad5 ebi d12mo ad6 l1 fb ad7 cb3 0.1 uf cb4 0.1 uf nwr avdd dvdd d12mi dvss cb8 0.1 uf dvss u4 m052_54 lqfp 48 m052_lqfp_48 ain1/t2/p1.1 44 ain2/rxd1/p1.2 45 ain3/txd1/p1.3 46 ain3/ss0/p1.4 47 p4.2 48 mosi_0/ain5/p1.5 1 miso_0/ain6/p1.6 2 sclk0/ain7/p1.7 3 vss 17 ldo_cap 18 p2.0/ad8/pwm0 19 p2.1/ad9/pwm1 20 p2.2/ad10/pwm2 21 p2.3/ad11/pwm3 22 p2.4/ad12/pwm4 23 p4.0 24 p2.6/ad14/pwm6 26 p4.6/ice_clk 30 p4.7/ice_dat 31 p0.7/ad7/sclk1 32 p0.6/ad6/miso_1 33 p0.5/ad5/mosi_1 34 p0.4/ad4/ss1 35 p4.1 36 p0.3/ad3/rts0 37 p0.2/ad2/cts0 38 p0.1/ad1/rts1 39 rst 4 rxd/p3.0 5 avss 6 mclk/int1/p3.3 9 txd/p3.1 7 int0/p3.2 8 sda/t0/p3.4 10 scl/t1/p3.5 11 p4.3 12 p3.6/wr/cko 13 p4.5/ale 29 p4.4/cs 28 ain0/t2/p1.0 43 avdd 42 vdd 41 p0.0/ad0/cts1 40 p3.7/rd 14 xtal1 16 xtal2 15 p2.5/ad13/pwm5 25 p2.7/ad15/pwm7 27 mosi_0 aa15 avss miso_0 sclk0 aa14 avss nticerst aa13 dvss p33 p41 l2 fb aa5 ad4 ticedat adc input ticeclk ale aa6 ncs cb5 0.1 uf dvdd dvdd dvss cb6 0.1 uf dvss ad15 u3 bs616lv4017eg70(tsop-44) a4 1 a3 2 a2 3 a1 4 a0 5 cs 6 i/o0 7 i/o1 8 i/o2 9 i/o3 10 vcc 11 vss 12 i/o4 13 i/o5 14 i/o6 15 i/o7 16 we 17 a17 18 a16 19 a15 20 a14 21 a13 22 nc 28 a8 27 a12 23 a11 24 a9 26 a10 25 i/o8 29 i/o9 30 i/o10 31 i/o11 32 vcc 33 vss 34 i/o12 35 i/o13 36 i/o14 37 i/o15 38 lb 39 ub 40 oe 41 a5 44 a6 43 a7 42 aa7 ad3 cb1 0.1 uf ad2 nrd title size document number rev date: sheet of application.dsn 1.0 m052_54 application circuit 1 1 thursday , august 19, 2010 c5 10uf tant-b ad1 ad0 dvdd ad12 ad11 ad10 ad9 ad8 ale ad15 ad14 ad13 cb2 0.1 uf aa10 aa9 aa8 p42 u2 74f373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oe 1 le 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 vcc 20 gnd 10 aa13 aa12 aa11 aa15 aa14 ad15 nss0 ad14 txd1 ad13 rxd1 ad12 p11 aa4 ad11 aa0 aa3 p43 aa1 ad10 aa2 c3 820pf aa2 ad9 aa3 aa1 aa4 ad8 aa0 aa5 ncs u1 74f373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oe 1 le 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 vcc 20 gnd 10 aa6 adc aa8 ad0 aa7 ad1 ice interface c1 10uf/10v tant-a dvdd aa9 r1 10k reset circuit ad2 x1 12mhz xtal3-1 c4 20p d12mo c2 20p d12mi crystal aa10 con1 1x2 header 1 1 2 2 uart_txd uart_rxd uart dvdd vdd net4 net5 net40 net3 net9 net8 net6 net7 vss r4 33 net10 r6 33 net12 net13 net11 u5 max232a sop16/150 c1+ 1 v+ 2 c1- 3 c2+ 4 c2- 5 v- 6 t2out 7 r2in 8 r2out 9 t2in 10 t1in 11 r1out 12 r1in 13 t1out 14 gnd 15 vcc 16 aa11 c7 1uf tant-a c6 1uf tant-a c9 1uf tant-a c8 1uf tant-a p1 db9-m ( ) db9l-hp 5 9 4 8 3 7 2 6 1 10 11 r3 33 r5 33 icejp1 header 5x2 header5x2 1 2 3 4 5 6 7 8 9 10 nticerst ticeclk ticedat
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 52 - revision v 1.01 8 electrical characteristics 8.1 absolute maximum ratings symbol parameter min max unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage vin v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta - 40 + 8 5 ? c storage temperature t st - 55 +150 ? c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 3 5 ma maximum current so urced by a i/o pin 3 5 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 53 - revision v 1.01 8.2 dc electrical characteristics ( v dd - v ss = 2.5~5.5 v, ta = 25 ? c, f osc = 50 mhz unless otherwise specified.) parameter sym. specification test conditions min. typ. max. unit operation voltage v dd 2.5 5.5 v v dd = 2 .5v ~ 5.5v up to 50 mhz ldo output voltage v ldo 1.7 1.8 1.9 v v dd 2. 5 v band g ap analog input v bg - 5 % 1.2 0 + 5 % v v dd = 2 .5v ~ 5.5v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 a v dd v operating current normal run mode @ 50 m h z idd1 20.6 ma v dd = 5.5v@50mhz, enable all ip and pll, xtal= 12mhz idd2 14.4 ma v dd =5.5v@50mhz, disable all ip and enable pll, xtal=12mhz idd3 18.9 ma v dd = 3 .3 v@50mhz, enable all ip and pll, xtal=12mhz idd4 12.8 ma v dd = 3 .3 v@50mhz, disable all ip and enable pll, xtal=12mhz operating current norma l run mode @ 22 mhz idd 5 6.2 ma v dd = 5.5v@ 22 mhz, enable all ip and irc22m , disable pll idd 6 3.4 ma v dd =5.5v@ 22 mhz, disable all ip and enable irc22m , disable pll idd 7 6.1 ma v dd = 3 .3 v@ 22 mhz, enable all ip and irc22m , disable pll idd 8 3.4 ma v dd = 3 .3 v@ 22 mhz, disable all ip and enable irc22m , disable pll operating current normal run mode @ 12mhz idd 9 5.3 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz idd 10 3.7 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xt al=12mhz idd 11 4.0 ma v dd = 3 .3 v@12mhz, enable all ip and disable pll, xtal=12mhz idd 12 2.3 ma v dd = 3 .3 v@12mhz, disable all ip and disable pll, xtal=12mhz
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 54 - revision v 1.01 parameter sym. specification test conditions min. typ. max. unit operating current normal run mode @ 4 m h z idd 13 3.4 ma v dd = 5.5v@4mhz, enable all ip and disable pll, xtal=4mhz idd1 4 2.6 ma v dd = 5.5v@4mhz, disable all ip and disable pll, xtal=4mhz idd1 5 2.0 ma v dd = 3 .3 v@4mhz, enable all ip and disable pll, xtal=4mhz idd1 6 1.3 ma v dd = 3 .3 v@4mhz, disable all ip and disable pll, xtal= 4mhz operating current normal run mode @ 10k hz idd 17 98.7 u a v dd = 5.5v@ 10k hz, enable all ip and irc10k , disable pll idd1 8 97.4 u a v dd = 5.5v@ 10k hz, disable all ip and enable irc10k , disable pll idd1 9 86.4 u a v dd = 3.3 v@ 10k hz, enable all ip and irc10k , disable pll idd 20 85.2 u a v dd = 3.3 v@ 10k hz, disable all ip and enable irc10k , disable pll operating current idle mode @ 50 m h z iidle 1 16.2 ma v dd = 5.5v@50 m h z, enable all ip and pll, xtal=12 mhz iidle2 10.0 ma v dd =5.5v@50 m h z, d isable all ip and enable pll, xtal=12 mhz iidle3 14.6 ma v dd = 3v@50 m h z, enable all ip and pll, xtal=12 mhz iidle4 8.5 ma v dd = 3v@50 m h z, disable all ip and enable pll, xtal=12 mhz operating current idle mode @ 22 mhz iidle5 4.3 ma v dd = 5.5v@ 22 mhz, enable all ip and irc22m , disable pll iidle6 1.5 ma v dd =5.5v@ 22 mhz, disable all ip and enable irc22m , disable pll iidle7 4.2 ma v dd = 3 .3 v@ 22 mhz, enable all ip and irc22m , disable pll iidle8 1.4 ma v dd = 3 .3 v@ 22 mhz, disable all ip a nd enable irc22m , disable pll operating current idle mode @ 12 m h z iidle 9 4.3 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz iidle 10 2.6 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xtal=12mhz
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 55 - revision v 1.01 parameter sym. specification test conditions min. typ. max. unit iidl e11 2.9 ma v dd = 3 .3 v @12mhz, enable all ip and disable pll, xtal=12mhz iidle 12 1.3 ma v dd = 3 .3 v@12mhz, disable all ip and disable pll, xtal=12mhz operating current idle mode @ 4 m h z iidle 13 3.0 ma v dd = 5.5v@4mhz, enable all ip and disable pll, xtal=4mhz iidle1 4 2.3 ma v dd = 5.5v@4mhz, disable all ip and disable pll, xtal=4mhz iidle1 5 1.7 ma v dd = 3 .3 v@4mhz, enable all ip and disable pll, xtal=4mhz iidle1 6 1.0 ma v dd = 3 .3 v@4mhz, disable all ip and disable pll, xtal=4mhz operating current idle mode @ 10khz iidle 17 97.8 u a v dd = 5.5v@ 10k hz, enable all ip and irc10k , disable pll iidle1 8 96.5 u a v dd = 5.5v@ 10k hz, disable all ip and enable irc10k , disable pll iidle1 9 85.5 u a v dd = 3.3 v@ 10k hz, enable all ip and irc10k , disable pll iidle 20 8 4.4 u a v dd = 3.3 v@ 10k hz, disable all ip and enable irc10k , disable pll standby current power - down mode (deep sleep mode) ipwd1 10 ? a v dd = 5.5v, no load @ disable bov function ipwd2 10 ? a v dd = 3. 0 v, no load @ disable bov function input current p 0/1/2/3/4 (quasi - bidirectional mode) i in1 - 75 - +15 ? a v dd = 5.5v, vin = 0v or vin= v dd input leakage current p 0/1/2/3/4 i lk - 1 - +1 ? a v dd = 5.5v, 0 numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 56 - revision v 1.01 parameter sym. specification test conditions min. typ. max. unit 2.4 - v d d +0.2 v dd = 3.0v negative going threshold (schmitt input), /rst v ils - 0.5 - 0. 2 v dd v positive going threshold (schmitt input), /rst v ihs 0. 7 v dd - v dd +0.5 v internal /rst pin pull up resistor rrst 4 0 1 5 0 k negative going threshold (schmitt inp ut), p 0/1/2/3/4 vils - 0.5 - 0. 3 v dd v positive going threshold (schmitt input), p 0/1/2/3/4 vihs 0. 7 v dd - v dd +0.5 v source current p 0/1/2/3/4 (quasi - bidirectional mode) i sr11 - 300 - 370 - 450 ? a v dd = 4.5v, v s = 2.4v i sr12 - 50 - 70 - 90 ? a v dd = 2.7v, v s = 2.2v i sr1 3 - 40 - 60 - 80 ? a v dd = 2.5v, v s = 2.0v source current p 0/1/2/3/4 (push - pull mode) i sr21 - 20 - 24 - 28 ma v dd = 4.5v, v s = 2.4 v i sr22 - 4 - 6 - 8 ma v dd = 2.7v, v s = 2.2v i sr2 3 - 3 - 5 - 7 ma v dd = 2.5v, v s = 2.0v sink current p 0/1/2/3/4 (quas i - bidirectional and push - pull mode) i sk1 1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 2 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 3 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - o ut voltage with bov_vl [1:0] =00b v bo2.2 2. 0 2.2 2. 4 v v dd = 5 .5v brown - o ut voltage wit h bov_vl [1:0] =01b v bo2.7 2. 5 2.7 2. 9 v v dd = 5 .5v brown - o ut voltage with bov_vl [1:0] =10b v bo3.8 3. 5 3. 7 3.9 v v dd = 5 .5v brown - o ut voltage with bov_vl [1:0] =11b v bo4.5 4. 1 4. 3 4. 5 v v dd = 5 .5v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2 .5v~5.5v notes: 1. /rst pin is a schmitt trigger input. 2. xtal1 is a cmos input. 3. pins of p0, p1, p2, p3 and p4 can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5v, 5 he transition current rea ches its maximum value when vin approximates to 2v .
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 57 - revision v 1.01 8.3 ac electrical characteristics 8.3.1 external crystal note: duty cycle is 50%. parameter symbol min. typ. max. units condition clock high time t chcx 20 - - ns clock low time t clcx 20 - - ns clock rise time t clch - - 10 ns clock fall time t chcl - - 10 ns 8.3.2 external oscillator parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - - 40 - 85 v dd - 2. 5 5 5.5 v operating c urrent 12 mhz@ v dd = 5v - 1 - ma t c l c l t c l c x t c h c x t c l c h t c h c l
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 58 - revision v 1.01 8.3.3 typical crystal application circuits crystal c1 c2 4 mhz ~ 24 mhz optional ( depend on crystal s pecification ) figure 8 - 1 typical crystal ap plication circuit x t a l 2 x t a l 1 c 1 c 2
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 59 - revision v 1.01 8.3.4 internal 22.1184 mhz rc oscillator parameter condition min. typ. max. unit center frequency - - 22. 1184 mhz calibrated internal oscillator frequency dd = 5 v - 3 - + 3 % - v dd =2. 5 v~ 5.5 v - 5 - + 5 % operating current v dd = 5 v - 500 - ua 8.3.5 internal 10 k hz rc oscillator parameter condition min. typ. max. unit supply voltage [1] - 2. 5 - 5.5 v center frequency - - 10 - k hz calibrated intern al oscillator frequency dd = 5 v - 30 - +30 % - v dd =2. 5 v~ 5.5 v - 50 - +50 % operating current v dd = 5 v - 5 - ua notes: 1. internal operation voltage comes f ro m ldo.
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 60 - revision v 1.01 8.4 analog characteristics 8.4.1 specification of 12 - bit saradc parameter sym. min. typ. max. unit resolution - - - 12 bit differential nonlinearity error dnl - 1.2 - lsb integral nonlinearity error inl - 1.2 - lsb offset error eo - +3 +5 lsb gain error (transfer gain) eg - - 4 - 6 - monotonic - guaranteed - adc clock frequenc y fadc - - 16 mhz conversion time tadc - 13 - clock sample rate fs - - 760 k sps supply voltage v l d o - 1.8 - v v a dd 3 - 5.5 v supply current (avg.) idd - 0.5 - ma idda - 1.5 - ma input voltage range vin 0 - a v dd v capacitance cin - 5 - pf
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 61 - revision v 1.01 8.4.2 spe cification of ldo & power management rameter min typ max unit note input voltage 2. 5 5 5.5 v v dd input voltage output voltage - 10% 1.8 +10% v ldo output voltage temperature - 40 25 85 c - 1 u - f resr=1ohm note: 1. it is recommended a 100nf bypass capac itor is connected between v dd and the closest v ss pin of the device. 2. for ensuring power stability, a 1 uf or higher capacitor must be connected between ldo pin and the closest v ss pin of the device.
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 62 - revision v 1.01 8.4.3 specification of low voltage reset parameter condition min. typ. max. unit operation voltage - 2.5 5 5.5 v temperature - - 40 25 85 quiescent current v dd =5.5v - - 5 ua threshold voltage temperature=25 1.7 2.0 2.3 v temperature= - 40 - 2. 3 - v temperature=85 - 1. 8 - v hysteresis - 0 0 0 v 8.4.4 specification of brown - o ut detector parameter condition min. typ. max. unit operati on voltage - 2.5 - 5.5 v quiescent current av dd =5.5v - - 1 40 a temperature - - 40 25 85 brown - o ut voltage bov_vl [1:0]=11 4. 1 4. 3 4. 5 v bov_vl [1:0]=10 3. 5 3. 7 3.9 v bov_vl [1:0]=01 2. 5 2. 7 2. 9 v bov_vl [1:0]=00 2. 0 2. 2 2. 4 v hysteresis - 30m - 150m v 8.4.5 specification of power - on reset (5v) parameter condition min. typ. max. unit temperature - - 40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 63 - revision v 1.01 8.4.6 specification of temperature sensor parameter conditions min. typ. max. unit supply voltage [1] 1.62 1.8 1.98 v temperature - 40 - 85 gain - 1.72 - 1.76 - 1.80 mv/ offset temp=0 717 725 733 mv note [1] : internal operation voltage comes from ldo. 8.4.7 specification of comparator parameter condition min. typ. max. unit temperature - - 40 25 85 v dd - 2.4 3 5.5 v v dd current - - 40 80 ua input offset voltage - 10 20 mv output swing - 0.1 - v dd - 0.1 v input common mode range - 0.1 - v dd - 0.1 v dc gain - - 70 - db propagation delay @vcm=1.2 v and vdiff=0.1 v - 200 - ns hysteresis @vcm=0.2 v ~ v dd - 0. 2 v - 10 - mv stable time @cinp=1.3 v cinn=1.2 v - - 2 us
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 64 - revision v 1.01 8.5 flash dc electrical characteristics symbol parameter conditions min. typ. max. unit n endu endurance 100000 cycles [1] t ret retention time temp= 85 10 year t erase page erase time 19 20 21 ms t mess mess erase time 30 40 50 ms t prog program time 38 40 42 us v dd supply voltage 1.62 1.8 1.98 v [2] i dd1 read current 0.25 ma i dd2 program/erase current 7 ma i pd power down current 1 20 ua 1. number of program/erase cycles. 2. v dd is source from chip ldo output voltage. 3. guaranteed by design, not test in production.
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 65 - revision v 1.01 9 p ackage dimensions 9.1 lqfp - 48 (7x7x1.4mm 2 f ootprint 2.0mm) 1 12 48 h h t controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 66 - revision v 1.01 9.2 qfn - 3 3 ( 5x5 mm 2 , thickness 0.8 mm , pitch 0.5 mm)
numicro ? m052/m054 bn data sheet publication release date: ma r. 19 , 20 12 - 67 - revision v 1.01 10 revision history version date page description v 1.0 0 oct 20 , 20 1 1 - i nitial i ssued v1.01 mar. 19, 2012 8.3.4 updated the center frequency of 22mhz rc spec
numicro ? m052/m054 bn data sheet publication release date: mar. 19 , 20 12 - 68 - revision v 1.01 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , insecure usage. insecure usage includes, but is not l imited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the da mages and liabilities thus incurred by nuvoton.

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